1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device with internal self-refreshing.
2. Description of Related Art
Semiconductor Dynamic Random Access Memory (known as DRAM) devices or "chips" have increased in capacity of at the rate of approximately quadruple every three years. With their increasing memory capacity, DRAM chips are widely used in several electronic devices such as portable personal computers, word processors, and printers. Customarily, Static Random Access Memory (SRAM) chips were used in such applications as portable personal computers and word processors, due to their small consumption of electrical power.
However, the use of DRAM chips instead of SRAM chips in these devices is desirable, since the cost of a DRAM chip is substantially less than the cost of an SRAM chip of equal memory capacity. DRAM devices are substantially less to fabricate than SRAM devices, since SRAM devices have a complex memory cell structure. It is well known that a DRAM device has one transistor per memory cell, while an SRAM chip typically uses either four or six transistors per cell. A further advantage of DRAM chips, is that since there is only one transistor per memory cell, a DRAM chip may have quadruple the memory capacity of a like dimensioned SRAM chip.
Despite the memory capacity advantages and low cost of fabricating DRAM devices, a disadvantage of DRAM chips, is that an external data refreshing signal is required to refresh and maintain data stored in the memory cells of the chip, while SRAM chips do not require an external data refresh signal. Thus, the timing waveforms of read data and write data cycles of these devices are different than SRAM devices, since they have a dedicated refresh time period. A further disadvantage of DRAM chips, is that due to the requirement of the external data refresh signal, DRAM devices typically consume more power than SRAM devices.
It therefore would be advantageous to provide a semiconductor memory device that combines the advantages of DRAM devices, such as high memory capacity, simple memory cell structure, and low cost, and SRAM devices, such as internal self-refreshing.
There have been number of attempts at achieving the above described advantages in the prior art. One such attempt is disclosed in U.S. Pat. No. 5,453,959, to Sakuta et al. The disclosed device comprises a semiconductor dynamic random access memory (DRAM) device equipped with a self-refreshing control circuit of a simplified structure. A counter circuit is provided for counting output pulses from a basic oscillator to produce first, second, and third counting outputs. A first detecting circuit, having a first programmable circuit, receives the first counting output from the counter circuit to detect that a predetermined signal input state continues for a set time period, set by the first programmable circuit.
A second detecting circuit receives the second counting output from the counter circuit to detect that refreshing of all memory cells has been completed. A third detecting circuit, having a second programmable circuit, receives the third counting output from the counter circuit to detect that a pause time set by the second programmable circuit has elapsed. The first to third detecting circuits are controlled by a control circuit. A disadvantage of the disclosed DRAM device is that it appears all memory cells in a block are simultaneously refreshed, which could slow down writing of data into the memory cells of the device.
U.S. Pat. No. 5,329,490, to Murotani, is directed to a dynamic semiconductor memory array device with refresh function. The disclosed memory cell array is divided into several memory cell array portions. Each memory cell array portion has a refresh period determined, so as to be adapted to a memory cell having minimum data retention time among memory cells therein. Thus, different memory cell array portions have different refresh periods. The disclosed device purportedly has the advantage over conventional memory cell arrays, where all memory cell array portions are refreshed with a common refresh period, in that consumption of electrical power by refresh can be enormously reduced relative to the conventional memory cell array. A disadvantage of the disclosed device, is that an external data refreshing signal must be applied to the device for data refreshing, thus the pin-out configuration of the device cannot match the pinout of an SRAM device.
A semiconductor memory device having self-refresh and back-bias circuitry is disclosed in U.S. Pat. No. 5,315,557, to Kim et al. A semiconductor memory device, such as a DRAM or pseudo-static RAM device, includes a self-refresh device that comprises a refresh timer for generating a refresh clock pulse, a binary counter for generating a predetermined number of signals of different frequencies in response to the refresh clock pulse, a circuit for generating a self-refresh enable signal in response to the signal transmitted from the binary counter. A back-bias clock pulse generator is also included having first, second, and third selectors, of which the third selector selects one of the signals transmitted from the binary counter in response to a signal output from each of the first and second selectors.
A back-bias generator having an oscillator and a back-bias voltage detecting circuit and selection circuit for receiving the output signal from the back-bias voltage detection circuit is attached thereto. A signal is transmitted to the oscillator in response to the self-refresh enable signal. The oscillator output, together with the output of the back-bias control pulse generator, causes a driver control circuit to feed a drive signal to a charge pump during a self-refresh operation. A disadvantage of the disclosed device, is that the external the self-refresh enable signal must be applied to the device to implement the self-refresh, and thus, the pin-out of the device is different than an SRAM device.
U.S. Pat. No. 5,033,026, to Tsujimoto, is directed to a pseudo-static RAM device which operates at a high speed in reading or writing mode and permits a long refreshing period in a self-refreshing mode. In the disclosed pseudo-static RAM device, an activation signal for enabling sense amplifiers is generated with a variable delay time, from a time point when a designated word line is driven. The delay time is switched in response to a control signal representing the self-refreshing mode. The delay time should be long enough to transfer 100% of the amount of information stored in the designated driven memory cell, to the bit line connected thereto. The delay time is maintained short when the control signal representing the self-refreshing mode is not present.
An apparent disadvantage common to the prior art, is that an external signal must be applied to the device to implement refreshing of data stored in the device's memory cells. Since the external refresh signal must be applied to the device, the pin-out configuration of prior art devices is different than the pin-out configuration of SRAM devices. Further since the external refresh signal must be applied to the device, the timing waveforms of these devices are different than SRAM devices. Therefore, these devices are not well suited for replacing SRAM chips in various applications, such as on an existing printed circuit board.
There, therefore exists a need for a semiconductor memory device that does not require that an external signal be applied to the device to implement data refreshing so that the device may replace an SRAM chip on an existing printed circuit board, and which has memory cells of a simple cell structure for high data storage capacity.